This invention relates to packet processing in switched fabric networks.
PCI (Peripheral Component Interconnect) Express is a serialized I/O interconnect standard developed to meet the increasing bandwidth needs of the next generation of computer systems. The PCI Special Interest Group (PCI-SIG) manages a number of PCI specifications, including the PCI Express Base Specification, Revision 1.0a, Apr. 15, 2003, as open industry standards, and provides the specifications to its members.
A PCI Express (“PCIe”) fabric includes a single host processor (also referred to as the “root complex”) that controls a global memory address space of a client system (e.g., desktops and laptops) or a server system (e.g., a workstation) having several PCIe devices. For client systems, these PCIe devices include, e.g., graphics, 1394, Gigabit Ethernet, and TV tuner cards. For server systems, the PCIe devices include Ultra320 SCSI RAID cards, Fibre Channel host bus adapters (HBAs), and 1- and 10-Gigabit Ethernet cards, to name a few. Upon power-up and enumeration process, the root complex interrogates the entire system by traversing through the hierarchical tree-topology and locates all PCIe devices that are connected in the system. An address space is allocated by the host processor for each PCIe device in the global memory address space in order for the host processor to communicate to it.
Two PCIe devices communicate by first passing data from an originating PCIe device up to the root complex through the address space allocated to the originating PCIe device. The data is then moved to the address space of a destination PCIe device by the host processor and subsequently traverses down to the destination PCIe device. Such communication is not considered to be a direct peer-to-peer relationship between the two PCIe devices but an indirect one managed by the host processor.
PCIe was designed to be fully compatible with the widely used PCI local bus standard. PCI is beginning to hit the limits of its capabilities, and while extensions to the PCI standard have been developed to support higher bandwidths and faster clock speeds, these extensions may be insufficient to meet the rapidly increasing bandwidth demands of PCs in the near future. With its high-speed and scalable serial architecture, PCIe may be an attractive option for use with or as a possible replacement for PCI in computer systems. PCIe is suited for providing scalability in systems with a single host processor with a number of PCIe devices. Since all communication is under the control of a single host processor, the PCIe architecture is generally not well suited for a large application space that includes multi-host and peer-to-peer communication.Advanced Switching (AS) is a technology which is based on the PCIe architecture, and which enables standardization of various backplane architectures. AS utilizes a packet-based transaction layer protocol that operates over the PCIe physical and data link layers. The AS architecture provides a number of features common to multi-host, peer-to-peer communication devices such as blade servers, clusters, storage arrays, telecom routers, and switches. These features include support for flexible topologies, packet routing, congestion management (e.g., credit-based flow control), fabric redundancy, and fail-over mechanisms. The Advanced Switching Interconnect Special Interest Group (ASI-SIG) is a collaborative trade organization chartered with providing a switching fabric interconnect standard, specifications of which, including the Advanced Switching Core Architecture Specification, Revision 1.0, December 2003 (available from the ASI-SIG at www.asi-sig.com), it provides to its members.